As miniaturization in recent large-scale-integration (LSI) manufacturing process advances and the voltage required in an LSI chip lowers, significant improvements, including decreasing chip area, increasing speed, and decreasing power consumption, have been achieved in the digital circuit field. Similar improvements, however, have not been achievable in the analog circuit field. Some factors preventing the advance in the analog circuit field include a decrease in transistor gain, an increase in characteristic variation, and an increase in leak current.
Therefore, in designing a ‘mixed signal IC (LSI),’ which is a combination of a digital circuit and an analog circuit, an approach is to minimize the use of analog circuits and/or ‘replace analog circuits with digital circuits.’
For example, a PLL circuit is used in a variety of applications, such as a clock generation circuit and a frequency synthesizer, but a charge pump and a loop filter each formed of a pure analog circuit are primarily responsible for preventing reduction in the area of a chip. Therefore, to reduce the area of a mixed signal IC, an All Digital Phase Locked Loop (ADPLL) circuit that replaces a conventional PLL circuit with a digital circuit is used.
In such an ADPLL circuit, in which a digital loop filter (DLF) is used, a phase frequency detector and a charge pump used in a PLL circuit are replaced with a time-to-digital converter (TDC). Further, a voltage controlled oscillator (VCO) is replaced with a digitally controlled oscillator (DCO).
For example, a TDC using a free-running oscillator (FROSC) is configured to include inverters having a ring structure and is advantageous in that linearity is more readily ensured than that in a TDC using single delay lines (SDL) (I. Nissinen, A. Mantyniemi, and J. Kostamovaara. A CMOS time-to-digital converter based on a ring oscillator for a laser radar. IEEE ESSCIRC, pages 469-472, April 2003).
Further, in order to achieve high resolution, a TDC using a multipath gated-ring oscillator (MPGRO) has been proposed (C. Hsu, M. Z. Straayer, and M. Perrot, “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise shaping time-to-digital converter and quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, December 2008). An MPGRO is configured to include a multipath that allows an input to each delay cell to be an output from an immediately preceding delay cell and an output from the delay cell upstream of the immediately preceding delay cell. Using the MPGRO allows noise-shaping-based improvement of adequate resolution. The noise shaping used herein is to drive quantization noise into a high-frequency region. Therefore, in such an ADPLL circuit, the combination of the noise shaping and the characteristics of a lowpass filter allows removal of phase noise in a loop bandwidth.
Further, it is possible to achieve high resolution of a TDC by using a time amplifier (TA) in a TDC (M. Lee and A. A. Abidi, “A 9b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue”, JSSC, vol. 43, no. 4, pp. 769-777, April, 2008). A TA is a circuit that amplifies a time difference between input signals, and then outputs the amplified time difference. For example, when a TA has a gain A, inputting an output from the TA to a TDC having a gate delay Tg achieves an effective resolution Tg/A.